MC9S08GT16A Datasheet, PDF (230/300 Pages) Freescale Semiconductor, Inc – Microcontrollers

Analog-to-Digital Converter (S08ATDV3)
14.4 Functional Description
The ATD uses a successive approximation register (SAR) architecture. The ATD contains all the necessary
elements to perform a single analog-to-digital conversion.
A write to the ATDSC register initiates a new conversion. A write to the ATDC register will interrupt the
current conversion but it will not initiate a new conversion. A write to the ATDPE register will also abort
the current conversion but will not initiate a new conversion. If a conversion is already running when a
write to the ATDSC register is made, it will be aborted and a new one will be started.
14.4.1 Mode Control
The ATD has a mode control unit to communicate with the sample and hold (S/H) machine and the SAR
machine when necessary to collect samples and perform conversions. The mode control unit signals the
S/H machine to begin collecting a sample and for the SAR machine to begin receiving a sample. At the
end of the sample period, the S/H machine signals the SAR machine to begin the analog-to-digital
conversion process. The conversion process is terminated when the SAR machine signals the end of
conversion to the mode control unit. For V_REFL and V_REFH, the SAR machine uses the reference potentials
to set the sampled signal level within itself without relying on the S/H machine to deliver them.
The mode control unit organizes the conversion, specifies the input sample channel, and moves the digital
output data from the SAR register to the result register. The result register consists of a dual-port register.
The SAR register writes data into the register through one port while the module data bus reads data out
of the register through the other port.
14.4.2 Sample and Hold
The S/H machine accepts analog signals and stores them as capacitor charge on a storage node located in
the SAR machine. Only one sample can be held at a time so the S/H machine and the SAR machine can
not run concurrently even though they are independent machines. Figure 14-10 shows the placement of the
various resistors and capacitors.
V_AIN
+
–
R_AS
C_AS
INPUT PIN _RAIN1
INPUT PIN
CHANNEL
SELECT 0
R_AIN2
INPUT PIN
CHANNEL
SELECT 1
R_AIN3
INPUT PIN
. CHANNEL
. SELECT 2
.
R_AINn
CHANNEL
SELECT n
C_AIN
ATD SAR
ENGINE
Figure 14-10. Resistor and Capacitor Placement
MC9S08GT16A/GT8A Data Sheet, Rev. 1
230
Freescale Semiconductor