MC9S08GT16A Datasheet, PDF (151/300 Pages) Freescale Semiconductor, Inc – Microcontrollers

Internal Clock Generator (S08ICGV4)
9.5.5 Example #4: Internal Clock Generator Trim
The internally generated clock source is guaranteed to have a period ± 25% of the nominal value. In some
cases, this may be sufficient accuracy. For other applications that require a tight frequency tolerance, a
trimming procedure is provided that will allow a very accurate source. This section outlines one example
of trimming the internal oscillator. Many other possible trimming procedures are valid and can be used.
Initial conditions:
1) Clock supplied from ATE has 500 µsec duty period
2) ICG configured for internal reference with 4 MHz bus
START TRIM PROCEDURE
ICGTRM = $80, n = 1
MEASURE
INCOMING CLOCK WIDTH
(COUNT = # OF BUS CLOCKS / 4)
COUNT < EXPECTED = 500
(RUNNING TOO SLOW)
CASE ST.ATEMENT ^{COUNT = EXPECTED = 500}
ICGTRM =
ICGTRM - 128 / (2**n)
(DECREASING ICGTRM
INCREASES THE FREQUENCY)
COUNT > EXPECTED = 500
(RUNNING TOO FAST)
ICGTRM =
ICGTRM + 128 / (2**n)
(INCREASING ICGTRM
DECREASES THE FREQUENCY)
STORE ICGTRM VALUE
IN NON-VOLATILE
MEMORY
n = n+1
CONTINUE
YES
IS n > 8?
NO
Figure 9-17. Trim Procedure
In this particular case, the MCU has been attached to a PCB and the entire assembly is undergoing final
test with automated test equipment. A separate signal or message is provided to the MCU operating under
user provided software control. The MCU initiates a trim procedure as outlined in Figure 9-17 while the
tester supplies a precision reference signal.
If the intended bus frequency is near the maximum allowed for the device, it is recommended to trim using
a reduction divisor (R) twice the final value. After the trim procedure is complete, the reduction divisor
can be restored. This will prevent accidental overshoot of the maximum clock frequency.
MC9S08GT16A/GT8A Data Sheet, Rev. 1
Freescale Semiconductor
151