MC9S08GT16A Datasheet, PDF (231/300 Pages) Freescale Semiconductor, Inc – Microcontrollers

Analog-to-Digital Converter (S08ATDV3)
When the S/H machine is not sampling, it disables its own internal clocks.The input analog signals are
unipolar. The signals must fall within the potential range of V_SSAD to V_DDAD. The S/H machine is not
required to perform special conversions (i.e., convert V_REFL and V_REFH).
Proper sampling is dependent on the following factors:
• Analog source impedance (the real portion, R_AS – see the electricals characteristics at the end of
this data sheet) — This is the resistive (or real, in the case of high frequencies) portion of the
network driving the analog input voltage V_AIN.
• Analog source capacitance (C_AS) — This is the filtering capacitance on the analog input, which (if
large enough) may help the analog source network charge the ATD input in the case of high R_AS.
• ATD input resistance (R_AIN – maximum value 7 kΩ) — This is the internal resistance of the ATD
circuit in the path between the external ATD input and the ATD sample and hold circuit. This
resistance varies with temperature, voltage, and process variation but a worst case number is
necessary to compute worst case sample error.
• ATD input capacitance (C_AIN – maximum value 25 pF) — This is the internal capacitance of the
ATD sample and hold circuit. This capacitance varies with temperature, voltage, and process
variation but a worst case number is necessary to compute worst case sample error.
• ATD conversion clock frequency (f_ATDCLK – maximum value 2 MHz) — This is the frequency of
the clock input to the ATD and is dependent on the bus clock frequency and the ATD prescaler.
This frequency determines the width of the sample window, which is 14 ATDCLK cycles.
• Input sample frequency (f_SAMP – see the electrical characteristics at the end of this data sheet) —
This is the frequency that a given input is sampled.
• Delta-input sample voltage (∆V_SAMP) — This is the difference between the current input voltage
(intended for conversion) and the previously sampled voltage (which may be from a different
channel). In non-continuous convert mode, this is assumed to be the greater of (V_REFH – V_AIN) and
(V_AIN – V_REFL). In continuous convert mode, 5 LSB should be added to the known difference to
account for leakage and other losses.
• Delta-analog input voltage (∆V_AIN) — This is the difference between the current input voltage and
the input voltage during the last conversion on a given channel. This is based on the slew rate of
the input.
In cases where there is no external filtering capacitance, the sampling error is determined by the number
of time constants of charging and the change in input voltage relative to the resolution of the ATD:
# of time constants (τ) = (14 / f_ATDCLK) / ((R_AS + R_AIN) * C_AIN)
sampling error in LSB (E_S) = 2^N * (∆V_SAMP / (V_REFH - V_REFL)) * e^−τ
The maximum sampling error (assuming maximum change on the input voltage) will be:
Eqn. 14-1
E_S = (3.6/3.6) * e^{–(14/((7 k + 10 k) * 50 p * 2 M))} * 1024 = 0.271 LSB
Eqn. 14-2
In the case where an external filtering capacitance is applied, the sampling error can be reduced based on
the size of the source capacitor (C_AS) relative to the analog input capacitance (C_AIN). Ignoring the analog
source impedance (R_AS), C_AS will charge C_AIN to a value of:
MC9S08GT16A/GT8A Data Sheet, Rev. 1
Freescale Semiconductor
231