MC9S08GT16A Datasheet, PDF (82/300 Pages) Freescale Semiconductor, Inc – Microcontrollers

Parallel Input/Output
6.2 External Signal Description
The MC9S08GT16A/GT8A has a total of 39 parallel I/O pins (one is output only) in six 8-bit ports
(PTA–PTE, PTG). Not all pins are bonded out in all packages. Consult the pin assignment in Chapter 2,
“Pins and Connections,” for available parallel I/O pins. All of these pins are available for general-purpose
I/O when they are not used by other on-chip peripheral systems.
After reset, BKGD/MS is enabled and therefore is not usable as an output pin until BKGDPE in SOPT is
cleared. The rest of the peripheral functions are disabled. After reset, all data direction and pullup enable
controls are set to 0s. These pins default to being high-impedance inputs with on-chip pullup devices
disabled.
The following paragraphs discuss each port and the software controls that determine each pin’s use.
6.2.1 Port A and Keyboard Interrupts
Port A
Bit 7
MCU Pin:
PTA7/
KBIP7
6
5
4
3
PTA6/ PTA5/ PTA4/ PTA3/
KBIP6 KBIP5 KBIP4 KBIP3
Figure 6-2. Port A Pin Names
2
PTA2/
KBIP2
1
PTA1/
KBIP1
Bit 0
PTA0/
KBIP0
Port A is an 8-bit port shared among the KBI keyboard interrupt inputs and general-purpose I/O. Any pins
enabled as KBI inputs will be forced to act as inputs.
Port A pins are available as general-purpose I/O pins controlled by the port A data (PTAD), data direction
(PTADD), pullup enable (PTAPE), and slew rate control (PTASE) registers. Refer to Section 6.3, “Parallel
I/O Controls,” for more information about general-purpose I/O control.
Port A can be configured to be keyboard interrupt input pins. Refer to Chapter 7, “Keyboard Interrupt
(S08KBIV1),” for more information about using port A pins as keyboard interrupts pins.
6.2.2 Port B and Analog to Digital Converter Inputs
j
Port B
Bit 7
MCU Pin:
PTB7/
ADP7
6
5
4
3
PTB6/
ADP6
PTB5/
ADP5
PTB4/
ADP4
PTB3/
ADP3
Figure 6-3. Port B Pin Names
2
PTB2/
ADP2
1
PTB1/
ADP1
Bit 0
PTB0/
ADP0
Port B is an 8-bit port shared among the ATD inputs and general-purpose I/O. Any pin enabled as an ATD
input will be forced to act as an input.
Port B pins are available as general-purpose I/O pins controlled by the port B data (PTBD), data direction
(PTBDD), pullup enable (PTBPE), and slew rate control (PTBSE) registers. Refer to Section 6.3, “Parallel
I/O Controls,” for more information about general-purpose I/O control.
When the ATD module is enabled, analog pin enables are used to specify which pins on port B will be used
as ATD inputs. Refer to Chapter 14, “Analog-to-Digital Converter (S08ATDV3),” for more information
about using port B pins as ATD pins.
MC9S08GT16A/GT8A Data Sheet, Rev. 1
82
Freescale Semiconductor