MC9S08GT16A Datasheet, PDF (88/300 Pages) Freescale Semiconductor, Inc – Microcontrollers

Parallel Input/Output
R
W
Reset
7
PTASE7
0
6
PTASE6
5
PTASE5
4
PTASE4
3
PTASE3
2
PTASE2
1
PTASE1
0
0
0
0
0
0
Figure 6-10. Slew Rate Control Enable for Port A (PTASE)
0
PTASE0
0
Table 6-3. PTASE Field Descriptions
Field
Description
7:0
PTASE[7:0]
Slew Rate Control Enable for Port A Bits — For port A pins that are outputs, these read/write control bits
determine whether the slew rate controlled outputs are enabled. For port A pins that are configured as inputs,
these bits are ignored.
0 Slew rate control disabled.
1 Slew rate control enabled.
R
W
Reset
7
PTADD7
0
6
PTADD6
5
PTADD5
4
PTADD4
3
PTADD3
2
PTADD2
0
0
0
0
0
Figure 6-11. Data Direction for Port A (PTADD)
1
PTADD1
0
0
PTADD0
0
Table 6-4. PTADD Field Descriptions
Field
Description
7:0
PTADD[7:0]
Data Direction for Port A Bits — These read/write bits control the direction of port A pins and what is read for
PTAD reads.
0 Input (output driver disabled) and reads return the pin value.
1 Output driver enabled for port A bit n and PTAD reads return the contents of PTADn.
MC9S08GT16A/GT8A Data Sheet, Rev. 1
88
Freescale Semiconductor