MC9S08GT16A Datasheet, PDF (37/300 Pages) Freescale Semiconductor, Inc – Microcontrollers

Modes of Operation
and this 1-kHz source are disabled. Power consumption is lower when the 1-kHz source is disabled, but in
that case the real-time interrupt cannot wake the MCU from stop.
3.5.4 Active BDM Enabled in Stop Mode
Entry into the active background mode from run mode is enabled if the ENBDM bit in BDCSCR is set.
This register is described in the Chapter 15, “Development Support,” section of this data sheet. If ENBDM
is set when the CPU executes a STOP instruction, the system clocks to the background debug logic remain
active when the MCU enters stop mode so background debug communication is still possible. In addition,
the voltage regulator does not enter its low-power standby state but maintains full internal regulation. If
the user attempts to enter either stop1 or stop2 with ENBDM set, the MCU will instead enter stop3.
Most background commands are not available in stop mode. The memory-access-with-status commands
do not allow memory access, but they report an error indicating that the MCU is in either stop or wait
mode. The BACKGROUND command can be used to wake the MCU from stop and enter active
background mode if the ENBDM bit is set. After the device enters background debug mode, all
background commands are available. The table below summarizes the behavior of the MCU in stop when
entry into the background debug mode is enabled.
Table 3-2. BDM Enabled Stop Mode Behavior
CPU, Digital
Mode PDC PPDC Peripherals, RAM
ICG
ATD
FLASH
Stop3 Don’t Don’t
care care
Standby
Standby
Active Disabled¹
1 _{Either ATD stop mode or power-down mode depending on the state of ATDPU.}
Regulator
Active
I/O Pins
States
held
RTI
Optionally on
3.5.5 LVD Enabled in Stop Mode
The LVD system is capable of generating either an interrupt or a reset when the supply voltage drops below
the LVD voltage. If the LVD is enabled in stop by setting the LVDE and the LVDSE bits in SPMSC1 when
the CPU executes a STOP instruction, then the voltage regulator remains active during stop mode. If the
user attempts to enter either stop1 or stop2 with the LVD enabled for stop (LVDSE = 1), the MCU will
instead enter stop3. The table below summarizes the behavior of the MCU in stop when the LVD is
enabled.
Table 3-3. LVD Enabled Stop Mode Behavior
CPU, Digital
Mode PDC PPDC Peripherals, RAM
ICG
ATD
FLASH
Stop3 Don’t Don’t
care care
Standby
Standby Standby Disabled¹
1 _{Either ATD stop mode or power-down mode depending on the state of ATDPU.}
Regulator
Active
I/O Pins
States
held
RTI
Optionally on
MC9S08GT16A/GT8A Data Sheet, Rev. 1
Freescale Semiconductor
37