I.MX27L_11 Datasheet, PDF (91/152 Pages) Freescale Semiconductor, Inc – Multimedia Applications Processor Multiple clock and power domains

Electrical Characteristics
SS23
SS22
SS26
SS25
SS24
DAM1_T_CLK
(Input)
SS28
DAM1_T_FS (bl)
(Input)
DAM1_T_FS (wl)
(Input)
DAM1_RXD
(Input)
SS30
SS32
SS35
SS40
SS41 SS36
SS34
Figure 52. SSI Receiver with External Clock Timing Diagram
Table 49. SSI Receiver with External Clock Timing Parameters
ID
Parameter
Min
Max
Unit
External Clock Operation
SS22 (Tx/Rx) CK clock period
SS23 (Tx/Rx) CK clock high period
SS24 (Tx/Rx) CK clock rise time
SS25 (Tx/Rx) CK clock low period
SS26 (Tx/Rx) CK clock fall time
SS28 (Rx) CK high to FS (bl) high
SS30 (Rx) CK high to FS (bl) low
SS32 (Rx) CK high to FS (wl) high
SS34 (Rx) CK high to FS (wl) low
SS35 (Tx/Rx) External FS rise time
SS36 (Tx/Rx) External FS fall time
SS40 SRXD setup time before (Rx) CK low
SS41 SRXD hold time after (Rx) CK low
81.4
36.0
—
36.0
—
–10.0
10.0
–10.0
10.0
—
—
10.0
2.0
—
ns
—
ns
6.0
ns
—
ns
6.0
ns
15.0
ns
—
ns
15.0
ns
—
ns
6.0
ns
6.0
ns
—
ns
—
ns
i.MX27 and i.MX27L Data Sheet, Rev. 1.7
Freescale Semiconductor
91