I.MX27L_11 Datasheet, PDF (33/152 Pages) Freescale Semiconductor, Inc – Multimedia Applications Processor Multiple clock and power domains

Pad Name
USBOTG_DATA0/Oen
USBOTG_DATA6/SPEED
USBOTG_DATA5/RCV
USBH1_RXDP
USBH1_RXDM
USBH1_TXDP
USBH1_TXDM
USBH1_OE_B
USBH1_FS
USBH1_RCV
USB_OC_B
USB_PWR
USBH1_SUSP
OE_ACD
CONTRAST
VSYNC
HSYNC
SPL_SPR
PS
CLS
REV
LD [17:0]
LSCLK
Signal Descriptions
Table 3. i.MX27/MX27L Signal Descriptions (continued)
Function/Notes
USB OTG data0/Output Enable signal; multiplexed with SLCDC1_DAT11 through PC9
USB OTG data6/Suspend signal; multiplexed with SLCDC1_DAT10 and USBG_TXR_INT_B
through PC8
USB OTG data5/RCV signal; multiplexed with SLCDC1_DAT9 through PC7
USB Host1 Receive Data Plus signal, multiplexed with UART4_RXD; multiplexed with
SLCDC1_DAT6 and UART4_RTS_ALT through PB31
USB Host1 Receive Data Minus signal; multiplexed with SLCDC1_DAT5 and UART4_CTS
through PB30
USB Host1 Transmit Data Plus signal; multiplexed with UART4_CTS, multiplexed with
SLCDC1_DAT4 and UART4_RXD_ALT through PB29
USB Host1 Transmit Data Minus signal; multiplexed with UART4_TXD, multiplexed with
SLCDC1_DAT3 through PB28
USB Host1 Output Enable signal; multiplexed with SLCDC1_DAT2 through PB27
USB Host1 Full Speed output signal, multiplexed with UART4_RTS, multiplexed with
SLCDC1_DAT1 through PB26
USB Host1 RCV signal; multiplexed with SLCDC1_DAT0 through PB25
USB OC signal. PB24
USB Power signal; PB23
USB Host1 Suspend signal; PB22
LCD Controller and Smart LCD Controller
Alternate Crystal Direction/Output Enable; PA31
This signal is used to control the LCD bias voltage as contrast control; PA30
Frame Sync or Vsync—This signal also serves as the clock signal output for gate;
driver (dedicated signal SPS for Sharp panel HR-TFT); PA29.
Line Pulse or HSync; PA28
Sampling start signal for left and right scanning. Through GPIO, this signal is multiplexed with
the SLCDC1_CLK; PA27.
Control signal output for source driver (Sharp panel dedicated signal). This signal is multiplexed
with the SLCDC1_CS; PA26.
Start signal output for gate driver. This signal is invert version of PS (Sharp panel dedicated
signal). This signal is multiplexed with the SLCDC1_RS; PA25.
Signal for common electrode driving signal preparation (Sharp panel dedicated signal). This
signal is multiplexed with SLCDC1_D0; PA24.
LCD Data Bus—All LCD signals are driven low after reset and when LCD is off. Through GPIO,
LD[15:0] signals are multiplexed with SLCDC1_DAT[15:0], SLCDC. PA23–PA6.
Shift Clock; PA5
i.MX27 and i.MX27L Data Sheet, Rev. 1.7
Freescale Semiconductor
33