I.MX27L_11 Datasheet, PDF (54/152 Pages) Freescale Semiconductor, Inc – Multimedia Applications Processor Multiple clock and power domains

Electrical Characteristics
4.3 Timing Diagrams
Figure 13 and Figure 14 depict the master mode and slave mode timing diagrams of the CSPI and Table 23
lists the timing parameters. The values shown in timing diagrams were tested using a worst case core
voltage of 1.1 V, slow pad voltage of 2.68 V, and fast pad voltage of 1.65 V.
SSn
(output)
t8
t6
CSPI1_RDY
(input)
t1
t2 t3
t7 t5
t9
SCLK
(output)
MOSI
t10 t11
t4 t4
MISO
t12 t13
SSn
(Input)
SCLK
(Input)
MISO
MOSI
Figure 13. CSPI Master Mode Timing Diagram
t7’ t5’
t6’
t1’
t10 t11
t12 t13
t2’ t3’
t4 t4
Figure 14. CSPI Slave Mode Timing Diagram
i.MX27 and i.MX27L Data Sheet, Rev. 1.7
54
Freescale Semiconductor