I.MX27L_11 Datasheet, PDF (61/152 Pages) Freescale Semiconductor, Inc – Multimedia Applications Processor Multiple clock and power domains

Electrical Characteristics
4.3.4 JTAG Controller (JTAGC)
This section details the electrical characteristics for the JTAGC module. Figure 22 shows the JTAGC test
clock input timing; Figure 23 shows the JTAGC boundary scan timing; Figure 24 shows the JTAGC test
access port; Figure 25 shows the JTAGC TRST timing; and Table 30 lists the JTAGC timing parameters.
J1
Tck
(input)
J2
J2
J3
J3
Figure 22. Test Clock Input Timing Diagram
TCK
(input)
Data
(inputs)
J5
J4
Input Data Valid
Data
(outputs)
J6
Output Data Valid
Data
(outputs)
Data
(outputs)
J7
J6
Output Data Valid
Figure 23. Boundary Scan Timing Diagram
i.MX27 and i.MX27L Data Sheet, Rev. 1.7
Freescale Semiconductor
61