I.MX27L_11 Datasheet, PDF (58/152 Pages) Freescale Semiconductor, Inc – Multimedia Applications Processor Multiple clock and power domains

Electrical Characteristics
Table 25. MII Receive Signal Timing Parameters (continued)
ID
Parameter¹
Min Max
Unit
M4
FEC_RX_CLK pulse width low
35% 65% FEC_RX_CLK period
Note:
1 _{FEC_RX_DV, FEC_RX_CLK, and FEC_RXD0 have the same timing in 10 Mbps 7-wire interface mode.}
4.3.2.2 MII Transmit Signal Timing (FEC_TXD[3:0], FEC_TX_EN, FEC_TX_ER,
and FEC_TX_CLK)
The transmitter functions correctly up to a FEC_TX_CLK maximum frequency of 25 MHz + 1%. There
is no minimum frequency requirement. In addition, the FEC IPG clock frequency must exceed twice the
FEC_TX_CLK frequency.
Figure 18 shows the MII transmit signal timings, and Table 26 lists the timing parameters.
M7
FEC_TX_CLK (input)
FEC_TXD[3:0] (outputs)
FEC_TX_EN
FEC_TX_ER
M5
M8
M6
Figure 18. MII Transmit Signal Timing Diagram
Table 26. MII Transmit Signal Timing Parameters
ID
Parameter¹
Min Max
Unit
M5 FEC_TX_CLK to FEC_TXD[3:0], FEC_TX_EN, FEC_TX_ER invalid
5
—
ns
M6 FEC_TX_CLK to FEC_TXD[3:0], FEC_TX_EN, FEC_TX_ER valid
— 20
ns
M7 FEC_TX_CLK pulse width high
35% 65% FEC_TX_CLK period
M8 FEC_TX_CLK pulse width low
35% 65% FEC_TX_CLK period
Note:
1 _{FEC_TX_EN, FEC_TX_CLK, and FEC_TXD0 have the same timing in 10 Mbps 7-wire interface mode.}
i.MX27 and i.MX27L Data Sheet, Rev. 1.7
58
Freescale Semiconductor