I.MX27L_11 Datasheet, PDF (80/152 Pages) Freescale Semiconductor, Inc – Multimedia Applications Processor Multiple clock and power domains

Electrical Characteristics
SDCLK
SDCLK
DQS (input)
DQ (input)
SD23
SD21
Data
SD22
Data
Data
Data
Data
Data
Data
Data
Figure 42. Mobile DDR SDRAM DQ versus DQS and SDCLK Read Cycle Timing Diagram
Table 42. Mobile DDR SDRAM Read Cycle Timing Parameters
ID
Parameter
SD21 DQS–DQ Skew (defines the Data valid window in read cycles related to DQS).
SD22 DQS DQ HOLD time from DQS
SD23 DQS output access time from SDCLK posedge
Symbol Min Max Unit
tDQSQ — 0.85 ns
tQH 2.3 — ns
tDQSCK — 6.7 ns
NOTE
SDRAM CLK and DQS related parameters are being measured from the
50% point—that is, high is defined as 50% of signal value and low is defined
as 50% of signal value.
The timing parameters are similar to the ones used in SDRAM data
sheets—that is, Table 42 indicates SDRAM requirements. All output signals
are driven by the ESDCTL at the negative edge of SDCLK and the
parameters are measured at maximum memory frequency.
4.3.9.1 SDHC Electrical DC Characteristics
Table 43 lists the SDHC electrical DC characteristics.
Table 43. SDHC Electrical DC Characteristics
ID
Parameter
General
SD10 Peak Voltage on All Lines
All Inputs
SD11 Input Leakage Current
All Outputs
SD12 Output Leakage Current
Power Supply
Min
Max
Unit
–0.3
–10
V_DD + 0.3
V
10
μA
–10
10
μA
Comments
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i.MX27 and i.MX27L Data Sheet, Rev. 1.7
80
Freescale Semiconductor