I.MX27L_11 Datasheet, PDF (67/152 Pages) Freescale Semiconductor, Inc – Multimedia Applications Processor Multiple clock and power domains

Signal
MSHC_BS
MSHC_DATA
Electrical Characteristics
Table 33. Serial Interface Timing Parameters (continued)
Parameter
Setup time
Hold time
Setup time
Hold time
Output delay time
Symbol
tBSsu
tBSh
tDsu
tDh
tDd
Standards
Unit
Min.
Max.
5
—
ns
5
—
ns
5
—
ns
5
—
ns
—
15
ns
Signal
MSHC_SCLK
MSHC_BS
MSHC_DATA
Table 34. Parallel Interface Timing Parameters
Parameter
Cycle
H pulse length
L pulse length
Rise time
Fall time
Setup time
Hold time
Setup time
Hold time
Output delay time
Symbol
tSCLKc
tSCLKwh
tSCLKwl
tSCLKr
tSCLKf
tBSsu
tBSh
tDsu
tDh
tDd
Standards
Min
Max
25
—
5
—
5
—
—
10
—
10
8
—
1
—
8
—
1
—
—
15
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4.3.7 NAND Flash Controller Interface (NFC)
Figure 31, Figure 32, Figure 33, and Figure 34 show the relative timing requirements among different
signals of the NFC at module level, and Table 35 lists the timing parameters. The NAND Flash Controller
(NFC) timing parameters are based on the internal NFC clock generated by the Clock Controller module,
where time T is the period of the NFC clock in ns. The relationship between the NFC clock and the external
timing parameters of the NFC is provided in Table 35.
Table 35 also provides two examples of external timing parameters with NFC clock frequencies of
22.17 MHz and 33.25 MHz. Assuming a 266 MHz FCLK (CPU clock), NFCDIV should be set to
divide-by-12 to generate a 22.17 MHz NFC clock and divide-by-8 to generate a 33.25 MHz NFC clock.
The user should compare the parameters of the selected NAND Flash memory with the NFC external
timing parameters to determine the proper NFC clock. The maximum NFC clock allowed is 66 MHz. It
should also be noted that the default NFC clock on power up is 16.63 MHz.
i.MX27 and i.MX27L Data Sheet, Rev. 1.7
Freescale Semiconductor
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