I.MX27L_11 Datasheet, PDF (60/152 Pages) Freescale Semiconductor, Inc – Multimedia Applications Processor Multiple clock and power domains

Electrical Characteristics
Table 28. MII Serial Management Channel Timing Parameters
ID
Parameter
M10 FEC_MDC falling edge to FEC_MDIO output invalid (minimum propagation delay)
M11 FEC_MDC falling edge to FEC_MDIO output valid (max propagation delay)
M12 FEC_MDIO (input) to FEC_MDC rising edge setup
M13 FEC_MDIO (input) to FEC_MDC rising edge hold
M14 FEC_MDC pulse width high
M15 FEC_MDC pulse width low
Min Max
Unit
0—
ns
—5
ns
18 —
ns
0—
ns
40% 60% FEC_MDC period
40% 60% FEC_MDC period
4.3.3 Inter IC Communication (I²C)
This section describes the electrical information of the I²C module.
4.3.3.1 I²C Module Timing
The I2C communication protocol consists of seven elements: START, Data Source/Recipient, Data
Direction, Slave Acknowledge, Data, Data Acknowledge, and STOP. Figure 21 shows the timing of the
I²C module. Table 29 lists the I2C module timing parameters.
SDA
IC5
IC3 IC4
SCL
IC1
IC2
IC6
Figure 21. I²C Bus Timing Diagram
Table 29. I2C Module Timing Parameters
ID
Parameter
—
SCL Clock Frequency
IC1
Hold time (repeated) START Condition
IC2
Data Hold Time
IC3
Data Setup Time
IC4
HIGH period of the SCL clock
IC5
LOW period of the SCL clock
IC6
Setup Time for STOP condition
1.8 V +/–0.10 V
Min
Max
0
100
114.8
—
0
69.7
3.1
—
69.7
—
336.4
—
110.5
—
3.0 V +/–0.30 V
Unit
Min
Max
0
111.1
0
1.76
68.3
335.1
111.1
100
kHz
—
ns
72.3
ns
—
ns
—
ns
—
ns
—
ns
i.MX27 and i.MX27L Data Sheet, Rev. 1.7
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Freescale Semiconductor