I.MX27L_11 Datasheet, PDF (88/152 Pages) Freescale Semiconductor, Inc – Multimedia Applications Processor Multiple clock and power domains

Electrical Characteristics
Table 47. SSI Receiver with Internal Clock Timing Parameters (continued)
ID
Parameter
SS49 Oversampling clock rise time
SS50 Oversampling clock low period
SS51 Oversampling clock fall time
Min
Max
Unit
—
3
ns
6
—
ns
—
3
ns
NOTE
All the timings for the SSI are given for a non-inverted serial clock polarity
(TSCKP/RSCKP = 0) and a non-inverted frame sync (TFSI/RFSI = 0). If the
polarity of the clock and/or the frame sync have been inverted, all the timing
remains valid by inverting the clock signal STCK/SRCK and/or the frame
sync STFS/SRFS shown in the tables and in the figures.
All timings are on AUDMUX pads when SSI is being used for data transfer.
“Tx” and “Rx” refer to the Transmit and Receive sections of the SSI.
For internal Frame Sync operation using external clock, the FS timing is the
same as that of Tx Data, for example, during the AC97 mode of operation.
4.3.11.3 SSI Transmitter Timing with External Clock
Figure 49 and Figure 50 show the SSI transmitter timing with external clock, and Table 48 lists the timing
parameters.
SS23
SS22
SS25
SS26
SS24
AD1_TXC
(Input)
SS27
SS29
AD1_TXFS (bl)
(Input)
AD1_TXFS (wl)
(Input)
AD1_TXD
(Output)
SS31
SS37
AD1_RXD
(Input)
Note: SRXD Input in Synchronous mode only
SS44
SS38
SS45
SS33
SS39
SS46
Figure 49. SSI Transmitter with External Clock Timing Diagram
i.MX27 and i.MX27L Data Sheet, Rev. 1.7
88
Freescale Semiconductor