I.MX27L_11 Datasheet, PDF (48/152 Pages) Freescale Semiconductor, Inc – Multimedia Applications Processor Multiple clock and power domains

Electrical Characteristics
One-Wire bus
(BATT_LINE)
OW8
OW7
OW9
Figure 7. Read Sequence Timing Diagram
Table 19. Write 1/Read Timing Parameters
ID
OW7
OW8
OW9
Parameter
Write 1/Read Low Time
Transmission Time Slot
Release Time
Symbol
Min
Typical
Max
Units
t_LOW1
1
t_SLOT
60
t_RELEASE
15
5
15
µs
117
120
µs
—
45
µs
4.2.3 ATA Electrical Specifications
This section describes the electrical information of the Parallel ATA module compliant with ATA/ATAPI-6
specification.
NOTE
The parallel ATA module is not available on the i.MX27L
Parallel ATA module can work on PIO/Multi-Word DMA/Ultra DMA transfer modes. Each transfer mode
has different data transfer rate, Ultra DMA mode 4 data transfer rate is up to 100 MB/s. Parallel ATA
module interface consist of a total of 29 pins, Some pins act on different function in different transfer
mode. There are different requirements of timing relationships among the function pins conform with
ATA/ATAPI-6 specification and these requirements are configurable by the ATA module registers.
Below defines the AC characteristics of all the interface signals on all data transfer modes.
4.2.3.1 General Timing Requirements
These are the general timing requirements for the ATA interface signals.
Table 20. AC Characteristics of All Interface Signals
ID
Parameter
Symbol
Min
SI1 Rising edge slew rate for any signal on ATA
S_rise
—
interface (see note)
SI2 Falling edge slew rate for any signal on ATA
S_fall
—
interface (see note)
Max
Unit
1.25
V/ns
1.25
V/ns
i.MX27 and i.MX27L Data Sheet, Rev. 1.7
48
Freescale Semiconductor