I.MX27L_11 Datasheet, PDF (13/152 Pages) Freescale Semiconductor, Inc – Multimedia Applications Processor Multiple clock and power domains

Functional Description and Application Information
• Statistic data generation for Auto Exposure (AE) and Auto White Balance (AWB) control of the
camera (for Bayer data only)
2.3.9 Configurable Serial Peripheral Interface (CSPI)
The Configurable Serial Peripheral Interface (CSPI) is used for fast data communication with fewer
software interrupts. There are three CSPI modules in the i.MX27/MX27L processors, which provide a
full-duplex synchronous serial interface, capable of interfacing to the SPI master and slave devices. CSPI1
and CSPI2 are master/slave configurable and include three chip selects to support multiple peripherals.
CSPI3 is only a master and has one chip-select signal. The transfer continuation function of the CSPI
enables unlimited length data transfers using 32-bit wide by 8-entry FIFO for both TX and RX data DMA
support.
The CSPI Ready (SPI_RDY) and Chip Select (SS) control signals enable fast data communication with
fewer software interrupts. When the CSPI module is configured as a master, it uses a serial link to transfer
data between the CSPI and an external device. A chip-enable signal and a clock signal are used to transfer
data between these two devices. When the CSPI module is configured as a slave, the user can configure
the CSPI Control register to match the external SPI master’s timing.
2.3.10 Direct Memory Access Controller (DMAC)
The Direct Memory Access Controller (DMAC) provides 16 channels to support linear memory, 2D
memory, FIFO, and end-of-burst enable FIFO transfers to support a wide variety of DMA operations.
Features include the following:
• Support of 16 channels linear memory, 2D memory, and FIFO for both source and destination
• Support of 8-bit, 16-bit, or 32-bit FIFO port size and memory port size data transfer
• Configurability of DMA burst length of up to a maximum of 16 words, 32 half-words, or 64 bytes
for each channel
• Bus utilization control for a channel that is not triggered by DMA request
• Interrupts that are provided to interrupt handler on bulk data transfer complete or transfer error
• DMA burst time-out error to terminate DMA cycle when the burst cannot be completed in a
programmed timing period
• Dedicated external DMA request and grant signal
• Support of increment, decrement, and no increment for source and destination addressing
• Support of DMA chaining
2.3.11 enhanced MultiMedia Accelerator Light (eMMA_lt)
The enhanced MultiMedia Accelerator Light (eMMA_lt) consists of the video pre-processor (PrP) and
post-processor (PP). In contrast with i.MX21 processor’s components, this eMMA does not include the
video codec. A more powerful video codec is included as a separate module.
NOTE
The i.MX27L does not have a eMMA_lt module.
i.MX27 and i.MX27L Data Sheet, Rev. 1.7
Freescale Semiconductor
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