I.MX27L_11 Datasheet, PDF (85/152 Pages) Freescale Semiconductor, Inc – Multimedia Applications Processor Multiple clock and power domains

Electrical Characteristics
SS1
SS5
SS3
SS2
SS4
DAM1_T_CLK
(Output)
SS6
DAM1_T_FS (bl)
(Output)
DAM1_T_FS (wl)
(Output)
DAM1_TXD
(Output)
DAM1_RXD
(Input)
SS8
SS10
SS16
SS14
SS17
SS12
SS15
SS18
SS43
SS42
SS19
Note: SRXD Input in Synchronous mode only
Figure 46. SSI Transmitter with Internal Clock Timing Diagram
Table 46. SSI Transmitter with Internal Clock Timing Parameters
ID
Parameter
Internal Clock Operation
SS1 (Tx/Rx) CK clock period
SS2 (Tx/Rx) CK clock high period
SS3 (Tx/Rx) CK clock rise time
SS4 (Tx/Rx) CK clock low period
SS5 (Tx/Rx) CK clock fall time
SS6 (Tx) CK high to FS (bl) high
SS8 (Tx) CK high to FS (bl) low
SS10 (Tx) CK high to FS (wl) high
SS12 (Tx) CK high to FS (wl) low
SS14 (Tx/Rx) Internal FS rise time
SS15 (Tx/Rx) Internal FS fall time
SS16 (Tx) CK high to STXD valid from high impedance
SS17 (Tx) CK high to STXD high/low
SS18 (Tx) CK high to STXD high impedance
SS19 STXD rise/fall time
Min
81.4
36.0
—
36.0
—
—
—
—
—
—
—
—
—
—
—
Max
Unit
—
ns
—
ns
6
ns
—
ns
6
ns
15.0
ns
15.0
ns
15.0
ns
15.0
ns
6
ns
6
ns
15.0
ns
15.0
ns
15.0
ns
6
ns
i.MX27 and i.MX27L Data Sheet, Rev. 1.7
Freescale Semiconductor
85