I.MX27L_11 Datasheet, PDF (64/152 Pages) Freescale Semiconductor, Inc – Multimedia Applications Processor Multiple clock and power domains

Electrical Characteristics
Table 31. LCDC Non-TFT Mode Timing Parameters
ID
Description
Min
T1 Pixel Clock period
22.5
T2 LP width
1
T3 LD setup time
5
T4 LD hold time
5
T5 Wait between LP and FLM rising edge
2
T6 Wait between last data and LP rising edge
1
Note:
1 _{T is pixel clock period.}
Max
Unit
1000
ns
—
T¹
—
ns
—
ns
—
T¹
—
T¹
VSYNC
HSYNC
Line 1 Line 2
Line n Line 1
HSYNC
OE
LSCLK
T2
T5
T1
T3 T4
LD
Figure 27. LCDC TFT Mode Timing Diagram
Table 32. LCDC TFT Mode Timing Parameters
ID
Description
Min
T1
Pixel Clock period
22.5
T2
HSYNC width
1
T3
LD setup time
5
T4
LD hold time
5
T5 Delay from the end of HSYNC to the beginning of the OE pulse.
3
T6
Delay from end of OE to the beginning of the HSYNC pulse.
1
T6
Ma
1000
—
—
—
—
—
Unit
ns
T¹
ns
ns
T¹
T¹
i.MX27 and i.MX27L Data Sheet, Rev. 1.7
64
Freescale Semiconductor