I.MX27L_11 Datasheet, PDF (87/152 Pages) Freescale Semiconductor, Inc – Multimedia Applications Processor Multiple clock and power domains

Electrical Characteristics
SS1
SS5
SS3
SS2
SS4
DAM1_T_CLK
(Output)
DAM1_T_FS (bl)
(Output)
DAM1_T_FS (wl)
(Output)
DAM1_RXD
(Input)
SS7 SS9
SS11
SS20
SS21
SS48
SS47
SS51
SS50
SS49
DAM1_R_CLK
(Output)
Figure 48. SSI Receiver with Internal Clock Timing Diagram
SS13
Table 47. SSI Receiver with Internal Clock Timing Parameters
ID
Parameter
Min
Max
Unit
Internal Clock Operation
SS1 (Tx/Rx) CK clock period
81.4
SS2 (Tx/Rx) CK clock high period
36.0
SS3 (Tx/Rx) CK clock rise time
—
SS4 (Tx/Rx) CK clock low period
36.0
SS5 (Tx/Rx) CK clock fall time
—
SS7 (Rx) CK high to FS (bl) high
—
SS9 (Rx) CK high to FS (bl) low
—
SS11 (Rx) CK high to FS (wl) high
—
SS13 (Rx) CK high to FS (wl) low
—
SS20 SRXD setup time before (Rx) CK low
10.0
SS21 SRXD hold time after (Rx) CK low
0
Oversampling Clock Operation
SS47 Oversampling clock period
SS48 Oversampling clock high period
15.04
6
—
ns
—
ns
6
ns
—
ns
6
ns
15.0
ns
15.0
ns
15.0
ns
15.0
ns
—
ns
—
ns
—
ns
—
ns
i.MX27 and i.MX27L Data Sheet, Rev. 1.7
Freescale Semiconductor
87