I.MX27L_11 Datasheet, PDF (130/152 Pages) Freescale Semiconductor, Inc – Multimedia Applications Processor Multiple clock and power domains

Package Information and Pinout
5.4 Pin Assignments (19 mm × 19 mm)
Table 61 shows the i.MX27 full 19 × 19 mm package MAPBGA pin assignment.
Table 62 identifies the pin assignments for the ball grid array (BGA) for full package. The connections of
these pins depend solely upon the user application, however there are a few factory test signals that are
not used in a normal application. Following is a list of these signals and how they are to be terminated for
proper operation of the i.MX27/MX27L processor:
• CLKMODE[1:0]: To ensure proper operation, leave these signals as no connects.
• OSC26M_TEST: To ensure proper operation, leave this signal as no connect.
• EXT_60M: To ensure proper operation, connect this signal to ground.
• EXT_266M: To ensure proper operation, connect this signal to ground.
• Most of the signals shown in Table 62 are multiplexed with other signals. For ease of reference, all
of the signals at a particular pad are shown in the form of a compound signal name. Refer to Table 3
for complete information on the signal multiplexing schemes of these signals.
i.MX27 and i.MX27L Data Sheet, Rev. 1.7
130
Freescale Semiconductor