I.MX27L_11 Datasheet, PDF (35/152 Pages) Freescale Semiconductor, Inc – Multimedia Applications Processor Multiple clock and power domains

Signal Descriptions
Table 3. i.MX27/MX27L Signal Descriptions (continued)
Pad Name
Function/Notes
Note: Both 1-Wire and Fast Ethernet Controller signals are multiplexed with other signals. As a result these signal names do not
appear in this list. The signals are listed below with the named signal that they are multiplexed.
1-Wire Signals:
The 1-Wire input and output signal is multiplexed with JTAG RTCK pad, PE16.
Fast Ethernet Controller (FEC) Signals on the i.MX27. The ATA module does not exist on the i.MX27L:
FEC_TX_EN: Transmit enable signal, through GPIO multiplexed with ATA_DATA15 pad; PF23
FEC_TX_ER: Transmit Data Error; through GPIO multiplexed with ATA_DATA14 pad; PD16
FEC_COL: Collision signal; through GPIO multiplexed with ATA_DATA13 pad; PD15
FEC_RX_CLK: Receive Clock signal; through GPIO multiplexed with ATA_DATA12 pad; PD14
FEC_RX_DV: Receive data Valid signal; through GPIO multiplexed with ATA_DATA11 pad; PD13
FEC_RXD0: Receive Data0; through GPIO multiplexed with ATA_DATA10 pad; PD12
FEC_TX_CLK: Transmit Clock signal; through GPIO multiplexed with ATA_DATA9 pad; PD11
FEC_CRS: Carrier Sense enable; through GPIO multiplexed with ATA_DATA8 pad; PD10
FEC_MDC: Management Data Clock; through GPIO multiplexed with ATA_DATA7 pad; PD9
FEC_MDIO: Management Data Input/Output, multiplexed with ATA_DATA6 pad; PD8
FEC_RXD3–1: Receive Data; through GPIO multiplexed with ATA_DATA5–3 pad; PD7–5
FEC_RX_ER: Receive Data Error; through GPIO multiplexed with ATA_DATA2 pad; PD4
FEC_TXD3–2: Transmit Data; through GPIO multiplexed with ATA_DATA1–0; pad; PD3–2
FEC_TXD1: Transmit Data; through GPIO multiplexed with SD3_CLK pad; PD1
FEC_TXD0: Transmit Data; through GPIO multiplexed with SD3_CMD pad; PD0
Note: The Rest ATA signals are multiplexed with PCMCIA Pads.
3.1 Power-Up Sequence
The i.MX27/MX27L processor consists of three major sets for power supply voltage named Q_VDD (core
logic supply), FUSE_VDD (analog supply for FUSEBOX), and N_VDD VDDA (IO supply). The External
Voltage Regulators and power-on devices must provide the applications processor with a specific sequence
of power and resets to ensure proper operation.
It is important that the applications processor power supplies be powered-up in a certain order to avoid
unintentional fuse blown. Q_VDD should be powered up before FUSE_VDD. The recommended order is:
1. Q_VDD(1.5 V)
2. FUSE_VDD (1.8 V) N_VDD (1.8/2.775 V), and Analog Supplies (2.775 V). See Table 3 for signal
descriptions.
or
1. Q_VDD (1.5 V), N_VDD (1.8/2.775 V), and Analog Supplies (2.775 V). See Table 3 for signal
descriptions.
2. FUSE_VDD (1.8 V).
3.2 EMI Pins Multiplexing
This section discusses the multiplexing of EMI signals. The EMI signals’ multiplexing is done inside the
EMI. Table 4 lists the i.MX27 pin names, pad types, and the memory devices’ equivalent pin names.
i.MX27 and i.MX27L Data Sheet, Rev. 1.7
Freescale Semiconductor
35