I.MX27L_11 Datasheet, PDF (77/152 Pages) Freescale Semiconductor, Inc – Multimedia Applications Processor Multiple clock and power domains

Electrical Characteristics
Table 39. SDRAM Refresh Timing Parameters (continued)
ID
SD3
SD6
SD7
SD10
SD11
Note:
Parameter
SDRAM clock cycle time
Address setup time
Address hold time
Precharge cycle period¹
Auto precharge command period¹
Symbol
tCK
tAS
tAH
tRP
tRC
Min
Max
7.5
—
1.8
—
1.8
—
1
4
2
20
1 _{SD10 and SD11 are determined by SDRAM controller register settings.}
Unit
ns
ns
ns
clock
clock
NOTE
SDR SDRAM CLK parameters are being measured from the 50%
point—that is, high is defined as 50% of signal value and low is defined as
50% of signal value.
The timing parameters are similar to the ones used in SDRAM data
sheets—that is, Table 39 indicates SDRAM requirements. All output signals
are driven by the ESDCTL at the negative edge of SDCLK and the
parameters are measured at maximum memory frequency.
i.MX27 and i.MX27L Data Sheet, Rev. 1.7
Freescale Semiconductor
77