I.MX27L_11 Datasheet, PDF (79/152 Pages) Freescale Semiconductor, Inc – Multimedia Applications Processor Multiple clock and power domains

Electrical Characteristics
SDCLK
SDCLK
DQS (output)
DQ (output)
SD19 SD20
SD17
SD18
Data Data
SD17
Data
Data
SD18
Data
Data
Data
Data
DQM (output)
DM
DM
DM
DM
DM
DM
DM
DM
SD17
SD18
SD17
SD18
Figure 41. Mobile DDR SDRAM Write Cycle Timing Diagram
Table 41. Mobile DDR SDRAM Write Cycle Timing Parameters¹
ID
Parameter
SD17 DQ and DQM setup time to DQS
SD18 DQ and DQM hold time to DQS
SD19 Write cycle DQS falling edge to SDCLK output delay time.
SD20 Write cycle DQS falling edge to SDCLK output hold time.
Note:
Symbol Min Max Unit
tDS
0.95 — ns
tDH
0.95 — ns
tDSS 1.8 — ns
tDSH 1.8 — ns
1 _{Test condition: Measured using delay line 5 programmed as follows: ESDCDLY5[15:0] = 0x0703.}
NOTE
SDRAM CLK and DQS related parameters are being measured from the
50% point—that is, high is defined as 50% of signal value and low is defined
as 50% of signal value.
The timing parameters are similar to the ones used in SDRAM data
sheets—that is, Table 41 indicates SDRAM requirements. All output signals
are driven by the ESDCTL at the negative edge of SDCLK and the
parameters are measured at maximum memory frequency.
i.MX27 and i.MX27L Data Sheet, Rev. 1.7
Freescale Semiconductor
79