I.MX27L_11 Datasheet, PDF (50/152 Pages) Freescale Semiconductor, Inc – Multimedia Applications Processor Multiple clock and power domains

Electrical Characteristics
Figure 9 shows sensor output data on the pixel clock falling edge. The CSI latches data on the pixel clock
rising edge.
1
VSYNC
7
HSYNC
PIXCLK
2
5
6
DATA[7:0]
Valid Data
3
4
Valid Data
Valid Data
Figure 9. CSI Timing Diagram, Gated, PIXCLK—Sensor Data at Falling Edge, Latch Data at Rising Edge
Figure 10 shows sensor output data on the pixel clock rising edge. The CSI latches data on the pixel clock
falling edge.
1
VSYNC
7
HSYNC
PIXCLK
2
5
6
DATA[7:0]
Valid Data
Valid Data
Valid Data
3
4
Figure 10. CSI Timing Diagram, Gated, PIXCLK—Sensor Data at Rising Edge, Latch Data at Falling Edge
i.MX27 and i.MX27L Data Sheet, Rev. 1.7
50
Freescale Semiconductor