I.MX27L_11 Datasheet, PDF (86/152 Pages) Freescale Semiconductor, Inc – Multimedia Applications Processor Multiple clock and power domains

Electrical Characteristics
Table 46. SSI Transmitter with Internal Clock Timing Parameters (continued)
ID
Parameter
Synchronous Internal Clock Operation
SS42 SRXD setup before (Tx) CK falling
SS43 SRXD hold after (Tx) CK falling
SS52 Loading
Min
Max
Unit
10.0
—
ns
0
—
ns
—
25
pF
• All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP/RSCKP = 0)
and a non-inverted frame sync (TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync
have been inverted, all the timing remains valid by inverting the clock signal STCK/SRCK and/or
the frame sync STFS/SRFS shown in the tables and in the figures.
• All timings are on AUDMUX pads when SSI is being used for data transfer.
• “Tx” and “Rx” refer to the Transmit and Receive sections of the SSI.
• For internal Frame Sync operation using external clock, the FS timing will be same as that of Tx
Data (for example, during AC97 mode of operation).
4.3.11.2 SSI Receiver Timing with Internal Clock
Figure 47 and Figure 48 show the SSI receiver timing with internal clock, and Table 47 lists the timing
parameters.
SS1
SS5
SS3
SS2
SS4
AD1_TXC
(Output)
SS7
AD1_TXFS (bl)
(Output)
AD1_TXFS (wl)
(Output)
AD1_RXD
(Input)
SS48
SS9
SS11
SS20
SS47
SS51
SS50
SS21
SS49
SS13
AD1_RXC
(Output)
Figure 47. SSI Receiver with Internal Clock Timing Diagram
i.MX27 and i.MX27L Data Sheet, Rev. 1.7
86
Freescale Semiconductor