I.MX27L_11 Datasheet, PDF (28/152 Pages) Freescale Semiconductor, Inc – Multimedia Applications Processor Multiple clock and power domains

Signal Descriptions
Pad Name
PC_CD1_B
PC_CD2_B
PC_WAIT_B
PC_READY
PC_PWRON
PC_VS1
PC_VS2
PC_BVD1
PC_BVD2
PC_RST
IOIS16
PC_RW_B
PC_POE
CLKO
EXT_60M
EXT_266M
OSC26M_TEST
RESET_IN
RESET_OUT
POR
XTAL26M
EXTAL26M
CLKMODE[1:0]
EXTAL32K
XTAL32K
Power_cut
Power_on_reset
28
Table 3. i.MX27/MX27L Signal Descriptions (continued)
Function/Notes
PCMCIA card detect signal, multiplexed with ATA ATA_DIOR signal; PF20
PCMCIA card detect signal, multiplexed with ATA ATA_DIOW signal; PF19
PCMCIA WAIT signal, multiplexed with ATA ATA_CS1 signal; PF18
PCMCIA READY/IRQ signal, multiplexed with ATA ATA_CS0 signal; PF17
PCMCIA signal, multiplexed with ATA ATA_DA2 signal; PF16
PCMCIA voltage sense signal, multiplexed with ATA ATA_DA1 signal; PF14
PCMCIA voltage sense signal, multiplexed with ATA ATA_DA0 signal; PF13
PCMCIA Battery voltage detect signal, multiplexed with ATA ATA_DMARQ signal; PF12
PCMCIA Battery voltage detect signal, multiplexed with ATA ATA_DMACK signalPF11
PCMCIA card reset signal, multiplexed with ATA ATA_RESET_B signal; PF10
PCMCIA mode signal, multiplexed with ATA ATA_INTRQ signal; PF9
PCMCIA read write signal, multiplexed with ATA ATA_IORDY signal; PF8
PCMCIA output enable signal, multiplexed with ATA ATA_BUFFER_EN signal; PF7
Clocks and Resets
Clock Out signal selected from internal clock signals. Refer to the clock controller for internal
clock selection; PF15.
This is a special factory test signal. To ensure proper operation, connect this signal to ground.
This is a special factory test signal. To ensure proper operation, connect this signal to ground.
This is a special factory test signal. To ensure proper operation, leave this signal as a no
connect.
Master Reset—External active low Schmitt trigger input signal. When this signal goes active,
all modules (except the reset module, SDRAMC module, and the clock control module) are
reset.
Reset_Out—Output from the internal Hreset_b; and the Hreset can be caused by all reset
source: power on reset, system reset (RESET_IN), and watchdog reset.
Power On Reset—Active low Schmitt trigger input signal. The POR signal is normally generated
by an external RC circuit designed to detect a power-up event.
Oscillator output to external crystal
Crystal input (26 MHz), or a 16 MHz to 32 MHz oscillator (or square-wave) input when internal
oscillator circuit is shut down.
These are special factory test signals. To ensure proper operation, do not connect to these
signals.
32 kHz crystal input (Note: in the RTC power domain)
Oscillator output to 32 kHz crystal (Note: in the RTC power domain)
(Note: in the RTC power domain)
(Note: in the RTC power domain)
i.MX27 and i.MX27L Data Sheet, Rev. 1.7
Freescale Semiconductor