MC908JL8CDWE Datasheet, PDF (87/212 Pages) Freescale Semiconductor, Inc – Microcontrollers

Functional Description
7.3.1 Entering Monitor Mode
Table 7-1 shows the pin conditions for entering monitor mode. As specified in the table, monitor mode
may be entered after a POR.
Communication at 9600 baud will be established provided one of the following sets of conditions is met:
1. If IRQ = V_TST:
– Clock on OSC1 is 4.9125MHz
– PTB3 = low
2. If IRQ = V_TST:
– Clock on OSC1 is 9.8304MHz
– PTB3 = high
3. If $FFFE and $FFFF are blank (contain $FF):
– Clock on OSC1 is 9.8304MHz
– IRQ = V_DD
Table 7-1. Monitor Mode Entry Requirements and Options
$FFFE
IRQ
and
$FFFF
OSC1 Clock⁽¹⁾
Bus Frequency
Comments
V_TST(2)
V_TST(1)
X
0011
4.9152 MHz
X
1011
9.8304 MHz
2.4576 MHz
2.4576 MHz
High voltage entry to monitor
mode.
9600 baud communication on
PTB0. COP disabled.
BLANK
V_DD
(contain X X X 1
9.8304 MHz
$FF)
2.4576 MHz
Blank reset vector
(low-voltage) entry to monitor
mode.
9600 baud communication on
PTB0. COP disabled.
V_DD
NOT
BLANK
XXXX
X
OSC1 ÷ 4
Enters User mode.
1. RC oscillator cannot be used for monitor mode; must use either external oscillator or XTAL oscillator circuit.
2. See Table 17-4 for V_TST voltage level requirements.
If V_TST is applied to IRQ and PTB3 is low upon monitor mode entry (Table 7-1 condition set 1), the bus
frequency is a divide-by-two of the clock input to OSC1. If PTB3 is high with V_TST applied to IRQ upon
monitor mode entry (Table 7-1 condition set 2), the bus frequency is a divide-by-four of the clock input to
OSC1. Holding the PTB3 pin low when entering monitor mode causes a bypass of a divide-by-two stage
at the oscillator only if V_TST is applied to IRQ. In this event, the OSCOUT frequency is equal to the
2OSCOUT frequency, and OSC1 input directly generates internal bus clocks. In this case, the OSC1
signal must have a 50% duty cycle at maximum bus frequency.
Entering monitor mode with V_TST on IRQ, the COP is disabled as long as V_TST is applied to either IRQ or
RST. (See Chapter 5 System Integration Module (SIM) for more information on modes of operation.)
If entering monitor mode without high voltage on IRQ and reset vector being blank ($FFFE and $FFFF)
(Table 7-1 condition set 3, where applied voltage is V_DD), then all port B pin requirements and conditions,
MC68HC908JL8/JK8 • MC68HC08JL8/JK8 • MC68HC908KL8 Data Sheet, Rev. 3.1
Freescale Semiconductor
87