MC908JL8CDWE Datasheet, PDF (178/212 Pages) Freescale Semiconductor, Inc – Microcontrollers

Low Voltage Inhibit (LVI)
15.4 LVI Control Register (CONFIG2/CONFIG1)
The LVI module is controlled by three bits in the configuration registers, CONFIG1 and CONFIG2.
Address: $001E
Bit 7
6
5
4
3
2
1
Read:
IRQPUD
R
R
LVIT1
LVIT0
R
R
Write:
Reset: 0
0
0
Cleared by POR only
0
0
Figure 15-2. Configuration Register 2 (CONFIG2)
Bit 0
STOP_
ICLKDIS
0
Address: $001F
Bit 7
6
Read:
COPRS
R
Write:
Reset: 0
0
5
4
3
2
1
R
LVID
R
SSREC STOP
0
0
0
0
0
Figure 15-3. Configuration Register 1 (CONFIG1)
Bit 0
COPD
0
LVID — Low Voltage Inhibit Disable Bit
LVID disables the LVI module. Reset clears LVID.
1 = Low voltage inhibit disabled
0 = Low voltage inhibit enabled
LVIT1, LVIT0 — LVI Trip Voltage Selection Bits
These two bits determine at which level of V_DD the LVI module will come into action. LVIT1 and LVIT0
are cleared by a power-on reset only.
Table 15-1. Trip Voltage Selection
LVIT1
LVIT0
Trip Voltage⁽¹⁾
0
0
V_LVR3 (2.49V)
0
1
V_LVR3 (2.49V)
1
0
V_LVR5 (4.25V)
1
1
Reserved
1. See Chapter 17 Electrical Specifications for full parameters.
Comments
For V_DD=3V operation
For V_DD=3V operation
For V_DD=5V operation
15.5 Low-Power Modes
The STOP and WAIT instructions put the MCU in low-power-consumption standby modes.
15.5.1 Wait Mode
The LVI module, when enabled, will continue to operate in wait mode.
15.5.2 Stop Mode
The LVI module, when enabled, will continue to operate in stop mode.
MC68HC908JL8/JK8 • MC68HC08JL8/JK8 • MC68HC908KL8 Data Sheet, Rev. 3.1
178
Freescale Semiconductor