MC908JL8CDWE Datasheet, PDF (164/212 Pages) Freescale Semiconductor, Inc – Microcontrollers

External Interrupt (IRQ)
The vector fetch or software clear may occur before or after the interrupt pin returns to logic one. As long
as the pin is low, the interrupt request remains pending. A reset will clear the latch and the MODE control
bit, thereby clearing the interrupt even if the pin stays low.
When set, the IMASK bit in the INTSCR mask all external interrupt requests. A latched interrupt request
is not presented to the interrupt priority logic unless the IMASK bit is clear.
NOTE
The interrupt mask (I) in the condition code register (CCR) masks all
interrupt requests, including external interrupt requests. (See 5.5 Exception
Control.)
RESET
ACK
IRQPUD
VECTOR
FETCH
DECODER
V_DD
INTERNAL
PULLUP
DEVICE
IRQ
V_DD
CLR
D
Q
CK
SYNCHRONIZER
TO CPU FOR
BIL/BIH
INSTRUCTIONS
IRQF
IRQ
INTERRUPT
REQUEST
IMASK
MODE
HIGH
VOLTAGE
DETECT
Figure 12-1. IRQ Module Block Diagram
TO MODE
SELECT
LOGIC
Addr.
$001D
Register Name
Bit 7
IRQ Status and Control ^{Read: 0}
Register Write:
(INTSCR) _{Reset: 0}
6
5
0
0
0
0
= Unimplemented
4
3
0
IRQF
0
0
Figure 12-2. IRQ I/O Register Summary
2
1
Bit 0
0
IMASK MODE
ACK
0
0
0
12.3.1 IRQ Pin
A logic zero on the IRQ pin can latch an interrupt request into the IRQ latch. A vector fetch, software clear,
or reset clears the IRQ latch.
If the MODE bit is set, the IRQ pin is both falling-edge-sensitive and low-level-sensitive. With MODE set,
both of the following actions must occur to clear IRQ:
MC68HC908JL8/JK8 • MC68HC08JL8/JK8 • MC68HC908KL8 Data Sheet, Rev. 3.1
164
Freescale Semiconductor