MC908JL8CDWE Datasheet, PDF (175/212 Pages) Freescale Semiconductor, Inc – Microcontrollers

COP Control Register
14.3.7 COPRS (COP Rate Select)
The COPRS signal reflects the state of the COP rate select bit (COPRS) in the configuration register 1.
Address: $001F
Bit 7
6
Read:
COPRS
R
Write:
5
4
3
2
1
R
LVID
R
SSREC STOP
Reset: 0
0
0
0
0
0
0
R
= Reserved
Figure 14-2. Configuration Register 1 (CONFIG1)
Bit 0
COPD
0
COPRS — COP Rate Select Bit
COPRS selects the COP timeout period. Reset clears COPRS.
1 = COP timeout period is (2¹³ – 2⁴) ICLK cycles
0 = COP timeout period is (2¹⁸ – 2⁴) ICLK cycles
COPD — COP Disable Bit
COPD disables the COP module.
1 = COP module disabled
0 = COP module enabled
14.4 COP Control Register
The COP control register is located at address $FFFF and overlaps the reset vector. Writing any value to
$FFFF clears the COP counter and starts a new timeout period. Reading location $FFFF returns the low
byte of the reset vector.
Address: $FFFF
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Low byte of reset vector
Write:
Clear COP counter
Reset:
Unaffected by reset
Figure 14-3. COP Control Register (COPCTL)
14.5 Interrupts
The COP does not generate CPU interrupt requests.
14.6 Monitor Mode
The COP is disabled in monitor mode when V_TST is present on the IRQ pin or on the RST pin.
14.7 Low-Power Modes
The WAIT and STOP instructions put the MCU in low-power consumption standby modes.
MC68HC908JL8/JK8 • MC68HC08JL8/JK8 • MC68HC908KL8 Data Sheet, Rev. 3.1
Freescale Semiconductor
175