MC908JL8CDWE Datasheet, PDF (76/212 Pages) Freescale Semiconductor, Inc – Microcontrollers

System Integration Module (SIM)
SBSW — SIM Break Stop/Wait
This status bit is useful in applications requiring a return to wait or stop mode after exiting from a break
interrupt. Clear SBSW by writing a logic zero to it. Reset clears SBSW.
1 = Stop mode or wait mode was exited by break interrupt
0 = Stop mode or wait mode was not exited by break interrupt
SBSW can be read within the break state SWI routine. The user can modify the return address on the
stack by subtracting one from it. The following code is an example of this. Writing zero to the SBSW bit
clears it.
; This code works if the H register has been pushed onto the stack in the break
; service routine software. This code should be executed at the end of the
; break service routine software.
HIBYTE EQU 5
LOBYTE EQU 6
;
If not SBSW, do RTI
BRCLR SBSW,BSR, RETURN ; See if wait mode or stop mode was exited
; by break.
TST LOBYTE,SP
; If RETURNLO is not zero,
BNE DOLO
; then just decrement low byte.
DEC HIBYTE,SP
; Else deal with high byte, too.
DOLO DEC LOBYTE,SP
; Point to WAIT/STOP opcode.
RETURN PULH
RTI
; Restore H register.
5.7.2 Reset Status Register (RSR)
This register contains six flags that show the source of the last reset. Clear the SIM reset status register
by reading it. A power-on reset sets the POR bit and clears all other bits in the register.
Address: $FE01
Bit 7
6
5
4
3
2
1
Bit 0
Read: POR
PIN
COP
ILOP
ILAD MODRST LVI
0
Write:
POR: 1
0
0
0
0
0
0
0
= Unimplemented
Figure 5-21. Reset Status Register (RSR)
POR — Power-On Reset Bit
1 = Last reset caused by POR circuit
0 = Read of RSR
MC68HC908JL8/JK8 • MC68HC08JL8/JK8 • MC68HC908KL8 Data Sheet, Rev. 3.1
76
Freescale Semiconductor