MC908JL8CDWE Datasheet, PDF (160/212 Pages) Freescale Semiconductor, Inc – Microcontrollers

Input/Output (I/O) Ports
11.4.3 Port D Control Register (PDCR)
The port D control register enables/disables the pull-up resistor and slow-edge high current capability of
pins PTD6 and PTD7.
Address:
Read:
Write:
Reset:
$000A
Bit 7
6
5
4
3
2
1
0
0
0
0
SLOWD7 SLOWD6 PTDPU7
0
0
0
0
0
0
0
Figure 11-13. Port D Control Register (PDCR)
Bit 0
PTDPU6
0
SLOWDx — Slow Edge Enable
The SLOWD6 and SLOWD7 bits enable the slow-edge, open-drain, high current output (25mA sink)
of port pins PTD6 and PTD7 respectively. DDRDx bit is not affected by SLOWDx.
1 = Slow edge enabled; pin is open-drain output
0 = Slow edge disabled; pin is push-pull (standard I/O)
PTDPUx — Port D Pull-up Enable Bits
The PTDPU6 and PTDPU7 bits enable the pull-up device on PTD6 and PTD7 respectively, regardless
the status of DDRDx bit.
1 = Enable pull-up device
0 = Disable pull-up device
11.5 Port E
Port E is a 2-bit special function port that shares its pins with the timer 2 interface module (see Chapter 8).
NOTE
PTE0–PTE1 are available on 32-pin packages only.
11.5.1 Port E Data Register (PTE)
The port E data register contains a data latch for each of the two port E pins.
Address:
Read:
Write:
Reset:
Alternative Functions:
$0008
Bit 7
6
5
4
3
2
Unaffected by reset
Figure 11-14. Port E Data Register (PTE)
1
PTE1
Bit 0
PTE0
T2CH1 T2CH0
PTE[1:0] — Port E Data Bits
These read/write bits are software programmable. Data direction of each port E pin is under the control
of the corresponding bit in data direction register E. Reset has no effect on port D data.
MC68HC908JL8/JK8 • MC68HC08JL8/JK8 • MC68HC908KL8 Data Sheet, Rev. 3.1
160
Freescale Semiconductor