MC908JL8CDWE Datasheet, PDF (146/212 Pages) Freescale Semiconductor, Inc – Microcontrollers

Analog-to-Digital Converter (ADC)
INTERNAL
DATA BUS
READ DDRB/DDRD
WRITE DDRB/DDRD
WRITE PTB/PTD
RESET
READ PTB/PTD
DDRBx/DDRDx
PTBx/PTDx
DISABLE
ADCx
ADC DATA REGISTER
DISABLE
ADC CHANNEL x
ADC0–ADC11 ADC12
INTERRUPT
LOGIC
CONVERSION
COMPLETE
AIEN COCO
BUS CLOCK
ADC
ADC VOLTAGE IN
ADCVIN
ADC CLOCK
CLOCK
GENERATOR
CHANNEL
SELECT
(1 OF 13 CHANNELS)
ADCH[4:0]
ADIV[2:0]
Figure 10-2. ADC Block Diagram
10.3.1 ADC Port I/O Pins
PTB0–PTB7 and PTD0–PTD3 are general-purpose I/O pins that are shared with the ADC channels. The
channel select bits (ADC status and control register, $003C), define which ADC channel/port pin will be
used as the input signal. The ADC overrides the port I/O logic by forcing that pin as input to the ADC. The
remaining ADC channels/port pins are controlled by the port I/O logic and can be used as
general-purpose I/O. Writes to the port register or DDR will not have any affect on the port pin that is
selected by the ADC. Read of a port pin which is in use by the ADC will return a logic 0 if the corresponding
DDR bit is at logic 0. If the DDR bit is at logic 1, the value in the port data latch is read.
MC68HC908JL8/JK8 • MC68HC08JL8/JK8 • MC68HC908KL8 Data Sheet, Rev. 3.1
146
Freescale Semiconductor