MC908JL8CDWE Datasheet, PDF (158/212 Pages) Freescale Semiconductor, Inc – Microcontrollers

Input/Output (I/O) Ports
11.4.1 Port D Data Register (PTD)
The port D data register contains a data latch for each of the eight port D pins.
Address: $0003
Bit 7
6
Read:
PTD7
Write:
PTD6
Reset:
Additional Functions
LED
(Sink)
LED
(Sink)
25mA sink 25mA sink
(Slow Edge) (Slow Edge)
pull-up pull-up
Alternative Functions: RxD
TxD
5
PTD5
T1CH1
4
3
PTD4
PTD3
Unaffected by reset
LED
(Sink)
T1CH0 ADC8
2
PTD2
LED
(Sink)
ADC9
Figure 11-10. Port D Data Register (PTD)
1
PTD1
ADC10
Bit 0
PTD0
ADC11
PTD[7:0] — Port D Data Bits
These read/write bits are software programmable. Data direction of each port D pin is under the control
of the corresponding bit in data direction register D. Reset has no effect on port D data.
ADC11–ADC8 — ADC channels 11 to 8
ADC[11:8] are pins used for the input channels to the analog-to-digital converter module. The channel
select bits, ADCH[4:0], in the ADC status and control register define which port pin will be used as an
ADC input and overrides any control from the port I/O logic. See Chapter 10 Analog-to-Digital
Converter (ADC).
T1CH1, T1CH0 — Timer 1 Channel I/Os
The T1CH1 and T1CH0 pins are the TIM1 input capture/output compare pins. The edge/level select
bits, ELSxB:ELSxA, determine whether the PTD4/T1CH0 and PTD5/T1CH1 pins are timer channel I/O
pins or general-purpose I/O pins. See Chapter 8 Timer Interface Module (TIM).
TxD, RxD — SCI Data I/O Pins
The TxD and RxD pins are the transmit data output and receive data input for the SCI module. The
enable SCI bit, ENSCI, in the SCI control register 1 enables the PTD6/TxD and PTD7/RxD pins as SCI
TxD and RxD pins and overrides any control from the port I/O logic. See Chapter 9 Serial
Communications Interface (SCI).
11.4.2 Data Direction Register D (DDRD)
Data direction register D determines whether each port D pin is an input or an output. Writing a logic 1 to
a DDRD bit enables the output buffer for the corresponding port D pin; a logic 0 disables the output buffer.
NOTE
For those devices packaged in a 20-pin package, PTD0–PTD1 and are not connected. DDRD0–DDRD1
should be set to a 1 to configure PTD0–PTD1 as outputs.
MC68HC908JL8/JK8 • MC68HC08JL8/JK8 • MC68HC908KL8 Data Sheet, Rev. 3.1
158
Freescale Semiconductor