MC908JL8CDWE Datasheet, PDF (138/212 Pages) Freescale Semiconductor, Inc – Microcontrollers

Serial Communications Interface (SCI)
9.8.3 SCI Control Register 3
SCI control register 3:
• Stores the ninth SCI data bit received and the ninth SCI data bit to be transmitted
• Enables these interrupts:
– Receiver overrun interrupts
– Noise error interrupts
– Framing error interrupts
• Parity error interrupts
Address: $0015
Bit 7
Read: R8
Write:
6
5
4
3
2
1
Bit 0
T8
DMARE DMATE ORIE
NEIE
FEIE
PEIE
Reset: U
U
0
0
0
0
0
0
= Unimplemented
U = Unaffected
Figure 9-11. SCI Control Register 3 (SCC3)
R8 — Received Bit 8
When the SCI is receiving 9-bit characters, R8 is the read-only ninth bit (bit 8) of the received character.
R8 is received at the same time that the SCDR receives the other 8 bits.
When the SCI is receiving 8-bit characters, R8 is a copy of the eighth bit (bit 7). Reset has no effect on
the R8 bit.
T8 — Transmitted Bit 8
When the SCI is transmitting 9-bit characters, T8 is the read/write ninth bit (bit 8) of the transmitted
character. T8 is loaded into the transmit shift register at the same time that the SCDR is loaded into
the transmit shift register. Reset has no effect on the T8 bit.
DMARE — DMA Receive Enable Bit
CAUTION
The DMA module is not included on this MCU. Writing a logic 1 to DMARE
or DMATE may adversely affect MCU performance.
1 = DMA not enabled to service SCI receiver DMA service requests generated by the SCRF bit (SCI
receiver CPU interrupt requests enabled)
0 = DMA not enabled to service SCI receiver DMA service requests generated by the SCRF bit (SCI
receiver CPU interrupt requests enabled)
DMATE — DMA Transfer Enable Bit
CAUTION
The DMA module is not included on this MCU. Writing a logic 1 to DMARE
or DMATE may adversely affect MCU performance.
1 = SCTE DMA service requests enabled; SCTE CPU interrupt requests disabled
0 = SCTE DMA service requests disabled; SCTE CPU interrupt requests enabled
ORIE — Receiver Overrun Interrupt Enable Bit
This read/write bit enables SCI error CPU interrupt requests generated by the receiver overrun bit, OR.
1 = SCI error CPU interrupt requests from OR bit enabled
0 = SCI error CPU interrupt requests from OR bit disabled
MC68HC908JL8/JK8 • MC68HC08JL8/JK8 • MC68HC908KL8 Data Sheet, Rev. 3.1
138
Freescale Semiconductor