MC908JL8CDWE Datasheet, PDF (42/212 Pages) Freescale Semiconductor, Inc – Microcontrollers

Configuration and Mask Option Registers (CONFIG & MOR)
3.3 Configuration Register 1 (CONFIG1)
Address: $001F
Bit 7
6
5
4
3
2
1
Read:
COPRS
R
Write:
R
LVID
R
SSREC STOP
Reset: 0
0
0
0
0
0
0
R
= Reserved
Figure 3-1. Configuration Register 1 (CONFIG1)
Bit 0
COPD
0
COPRS — COP Rate Select Bit
COPRS selects the COP time-out period. Reset clears COPRS.
(See Chapter 14 Computer Operating Properly (COP).)
1 = COP timeout period is (2¹³ – 2⁴) ICLK cycles
0 = COP timeout period is (2¹⁸ – 2⁴) ICLK cycles
LVID — Low Voltage Inhibit Disable Bit
LVID disables the LVI module. Reset clears LVID.
(See Chapter 15 Low Voltage Inhibit (LVI).)
1 = Low voltage inhibit disabled
0 = Low voltage inhibit enabled
SSREC — Short Stop Recovery Bit
SSREC enables the CPU to exit stop mode with a delay of
32 ICLK cycles instead of a 4096 ICLK cycle delay.
1 = Stop mode recovery after 32 ICLK cycles
0 = Stop mode recovery after 4096 ICLK cycles
NOTE
Exiting stop mode by pulling reset will result in the long stop recovery.
If using an external crystal, do not set the SSREC bit.
STOP — STOP Instruction Enable Bit
STOP enables the STOP instruction.
1 = STOP instruction enabled
0 = STOP instruction treated as illegal opcode
COPD — COP Disable Bit
COPD disables the COP module. Reset clears COPD.
(See Chapter 14 Computer Operating Properly (COP).)
1 = COP module disabled
0 = COP module enabled
MC68HC908JL8/JK8 • MC68HC08JL8/JK8 • MC68HC908KL8 Data Sheet, Rev. 3.1
42
Freescale Semiconductor