MC908AB32CFUE Datasheet, PDF (362/392 Pages) Freescale Semiconductor, Inc – Microcontrollers

Low-Voltage Inhibit (LVI)
21.5 LVI Status Register (LVISR)
The LVI status register flags V_DD voltages below the LVI_TRIPF level.
Address: $FE0F
Bit 7
6
5
4
3
2
1
Bit 0
Read: LVIOUT
0
0
0
0
0
0
0
Write:
Reset: 0
0
0
0
0
0
0
0
= Unimplemented
Figure 21-3. LVI Status Register (LVISR)
LVIOUT — LVI Output Bit
This read-only flag becomes set when V_DD falls below the LVI_TRIPF
voltage for 32 to 40 CGMXCLK cycles. (See Table 21-1.) Reset
clears the LVIOUT bit.
Table 21-1. LVIOUT Bit Indication
V_DD
At level:
For number of CGMXCLK
cycles:
V_DD > LVI_TRIPR
Any
V_DD < LVI_TRIPF
V_DD < LVI_TRIPF
V_DD < LVI_TRIPF
LVI_TRIPF < V_DD < LVI_TRIPR
< 32 CGMXCLK cycles
32 to 40 CGMXCLK cycles
> 40 CGMXCLK cycles
Any
LVIOUT
0
0
0 or 1
1
Previous value
21.6 LVI Interrupts
The LVI module does not generate interrupt requests.
Technical Data
362
Low-Voltage Inhibit (LVI)
MC68HC908AB32 — Rev. 1.1
Freescale Semiconductor