MC908AB32CFUE Datasheet, PDF (202/392 Pages) Freescale Semiconductor, Inc – Microcontrollers

Timer Interface Module B (TIMB)
12.5.3.2 Buffered Output Compare
Channels 0 and 1 can be linked to form a buffered output compare
channel whose output appears on the PTF4/TBCH0 pin. The TIMB
channel registers of the linked pair alternately control the output.
Setting the MS0B bit in TIMB channel 0 status and control register
(TBSC0) links channel 0 and channel 1. The output compare value in the
TIMB channel 0 registers initially controls the output on the
PTF4/TBCH0 pin. Writing to the TIMB channel 1 registers enables the
TIMB channel 1 registers to synchronously control the output after the
TIMB overflows. At each subsequent overflow, the TIMB channel
registers (0 or 1) that control the output are the ones written to last.
TBSC0 controls and monitors the buffered output compare function, and
TIMB channel 1 status and control register (TBSC1) is unused. While the
MS0B bit is set, the channel 1 pin, PTF5/TBCH1, is available as a
general-purpose I/O pin.
Channels 2 and 3 can be linked to form a buffered output compare
channel whose output appears on the PTF2/TBCH2 pin. The TIMB
channel registers of the linked pair alternately control the output.
Setting the MS2B bit in TIMB channel 2 status and control register
(TBSC2) links channel 2 and channel 3. The output compare value in the
TIMB channel 2 registers initially controls the output on the
PTF2/TBCH2 pin. Writing to the TIMB channel 3 registers enables the
TIMB channel 3 registers to synchronously control the output after the
TIMB overflows. At each subsequent overflow, the TIMB channel
registers (2 or 3) that control the output are the ones written to last.
TBSC2 controls and monitors the buffered output compare function, and
TIMB channel 3 status and control register (TBSC3) is unused. While the
MS2B bit is set, the channel 3 pin, PTF3/TBCH3, is available as a
general-purpose I/O pin.
NOTE:
In buffered output compare operation, do not write new output compare
values to the currently active channel registers. Writing to the active
channel registers is the same as generating unbuffered output
compares.
Technical Data
202
Timer Interface Module B (TIMB)
MC68HC908AB32 — Rev. 1.1
Freescale Semiconductor