MC908AB32CFUE Datasheet, PDF (112/392 Pages) Freescale Semiconductor, Inc – Microcontrollers

System Integration Module (SIM)
Addr.
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
Read:
SBSW
$FE00
SIM
Break
Status
Register
(SBSR)
Write:
R
R
R
R
R
R
R
Note
Reset: 0
0
0
0
0
0
0
0
Note: Writing a logic 0 clears SBSW.
Read: POR
PIN
COP
ILOP
ILAD
0
LVI
0
$FE01
SIM
Reset
Status
Register
(SRSR)
Write:
POR: 1
0
0
0
0
0
0
0
SIM Break Flag Control ^Read: _BCFE
R
R
R
R
R
R
R
$FE03
Register Write:
(SBFCR) _{Reset: 0}
= Unimplemented
R = Reserved
Figure 8-2. SIM I/O Register Summary
8.3 SIM Bus Clock Control and Generation
The bus clock generator provides system clock signals for the CPU and
peripherals on the MCU. The system clocks are generated from an
incoming clock, CGMOUT, as shown in Figure 8-3. This clock can come
from either an external oscillator or from the on-chip PLL.
See Section 9. Clock Generator Module (CGM).
OSC1
CLOCK
SELECT
÷2
CGMVCLK CIRCUIT
PLL
BCS
PTC3
MONITOR MODE
USER MODE
CGM
CGMXCLK
A
CGMOUT
B _S*
*When S = 1,
CGMOUT = B
Figure 8-3. CGM Clock Signals
Technical Data
112
System Integration Module (SIM)
SIM COUNTER
÷2
BUS CLOCK
GENERATORS
SIM
MC68HC908AB32 — Rev. 1.1
Freescale Semiconductor