MC908AB32CFUE Datasheet, PDF (317/392 Pages) Freescale Semiconductor, Inc – Microcontrollers

Input/Output (I/O) Ports
DDRA[7:0] — Data Direction Register A Bits
These read/write bits control port A data direction. Reset clears
DDRA[7:0], configuring all port A pins as inputs.
1 = Corresponding port A pin configured as output
0 = Corresponding port A pin configured as input
NOTE:
Avoid glitches on port A pins by writing to the port A data register before
changing data direction register A bits from 0 to 1. Figure 17-4 shows
the port A I/O logic.
READ DDRA ($0004)
WRITE DDRA ($0004)
RESET
WRITE PTA ($0000)
DDRAx
PTAx
PTAx
READ PTA ($0000)
Figure 17-4. Port A I/O Circuit
When DDRAx is a logic 1, reading address $0000 reads the PTAx data
latch. When DDRAx is a logic 0, reading address $0000 reads the
voltage level on the pin. The data latch can always be written, regardless
of the state of its data direction bit.
Table 17-2 summarizes the operation of the port A pins.
Table 17-2. Port A Pin Functions
DDRA
Bit
0
PTA Bit
X⁽¹⁾
I/O Pin Mode
Input, Hi-Z⁽²⁾
Accesses to DDRA
Read/Write
DDRA[7:0]
1
X
Output
DDRA[7:0]
Notes:
1. X = don’t care.
2. Hi-Z = high impedance.
3. Writing affects data register, but does not affect input.
Accesses to PTA
Read
Pin
Write
PTA[7:0]⁽³⁾
PTA[7:0] PTA[7:0]
MC68HC908AB32 — Rev. 1.1
Freescale Semiconductor
Input/Output (I/O) Ports
Technical Data
317