MC908AB32CFUE Datasheet, PDF (160/392 Pages) Freescale Semiconductor, Inc – Microcontrollers

Monitor ROM (MON)
10.4.1 Entering Monitor Mode
Table 10-1 shows the pin conditions for entering monitor mode.
Table 10-1. Monitor Mode Entry Conditions
IRQ Pin
CGMOUT
Bus Frequency
(CGMOUT ÷ 2)
V_TST(1)
CGMXCLK ÷ 2
1011
or
CGMVCLK ÷ 2
V_TST
1010
CGMXCLK
Notes:
1. For V_TST, see Section 23. Electrical Specifications.
CGMXCLK ÷ 4
or
CGMVCLK ÷ 4
CGMXCLK ÷ 2
Enter monitor mode by either
• Executing a software interrupt instruction (SWI) or
• Applying a logic 0 and then a logic 1 to the RST pin.
The MCU sends a break signal (10 consecutive logic 0s) to the host
computer, indicating that it is ready to receive a command. The break
signal also provides a timing reference to allow the host to determine the
necessary baud rate.
Monitor mode uses alternate vectors for reset, SWI, and break interrupt.
The alternate vectors are in the $FE page instead of the $FF page and
allow code execution from the internal monitor firmware instead of user
code. The COP module is disabled in monitor mode as long as V_TST (see
Section 23. Electrical Specifications) is applied to either the IRQ pin
or the RST pin. (See Section 8. System Integration Module (SIM) for
more information on modes of operation.)
NOTE:
Holding the PTC3 pin low when entering monitor mode causes a bypass
of a divide-by-two stage at the oscillator. The CGMOUT frequency is
equal to the CGMXCLK frequency, and the OSC1 input directly
generates internal bus clocks. In this case, the OSC1 signal must have
a 50% duty cycle at maximum bus frequency.
Technical Data
160
Monitor ROM (MON)
MC68HC908AB32 — Rev. 1.1
Freescale Semiconductor