MC908AB32CFUE Datasheet, PDF (192/392 Pages) Freescale Semiconductor, Inc – Microcontrollers

Timer Interface Module A (TIMA)
OVERFLOW
OVERFLOW
PERIOD
TACHx
OVERFLOW
OVERFLOW
OVERFLOW
CHxMAX
OUTPUT
COMPARE
OUTPUT
COMPARE
OUTPUT
COMPARE
OUTPUT
COMPARE
Figure 11-13. CHxMAX Latency
11.10.5 TIMA Channel Registers
These read/write registers contain the captured TIMA counter value of
the input capture function or the output compare value of the output
compare function. The state of the TIMA channel registers after reset is
unknown.
In input capture mode (MSxB:MSxA = 0:0), reading the high byte of the
TIMA channel x registers (TACHxH) inhibits input captures until the low
byte (TACHxL) is read.
In output compare mode (MSxB:MSxA ≠ 0:0), writing to the high byte of
the TIMA channel x registers (TACHxH) inhibits output compares until
the low byte (TACHxL) is written.
Address: $0027
Bit 7
6
Read:
Bit 15
14
Write:
Reset:
5
4
3
2
13
12
11
10
Indeterminate after reset
1
Bit 0
9
Bit 8
Figure 11-14. TIMA Channel 0 Register High (TACH0H)
Address: $0028
Bit 7
6
Read:
Bit 7
6
Write:
Reset:
5
4
3
2
5
4
3
2
Indeterminate after reset
1
Bit 0
1
Bit 0
Figure 11-15. TIMA Channel 0 Register Low (TACH0L)
Technical Data
192
Timer Interface Module A (TIMA)
MC68HC908AB32 — Rev. 1.1
Freescale Semiconductor