MC908AB32CFUE Datasheet, PDF (155/392 Pages) Freescale Semiconductor, Inc – Microcontrollers

Clock Generator Module (CGM)
9.10.4 Reaction Time Calculation
The actual acquisition and lock times can be calculated using the
equations below. These equations yield nominal values under the
following conditions:
• Correct selection of filter capacitor, C_F,
(see 9.10.3 Choosing a Filter Capacitor)
• Room temperature operation
• Negligible external leakage on CGMXFC
• Negligible noise
The K factor in the equations is derived from internal PLL parameters.
K_ACQ is the K factor when the PLL is configured in acquisition mode, and
K_TRK is the K factor when the PLL is configured in tracking mode. See
9.4.2.2 Acquisition and Tracking Modes.
t_ACQ
=


V--f--_{R-D--D-D--V-A-}


-K----_A-8--_C---_Q- _
t_AL
=


V--f--_{R-D--D-D--V-A-}


K-----_T^4--_R^----_K^{-}
t_LOCK = t_ACQ + t_AL
Note the inverse proportionality between the lock time and the reference
frequency.
In automatic bandwidth control mode the acquisition and lock times are
quantized into units based on the reference frequency. See 9.4.2.3
Manual and Automatic PLL Bandwidth Modes. A certain number of
clock cycles, n_ACQ, is required to ascertain whether the PLL is within the
tracking mode entry tolerance ∆_TRK, before exiting acquisition mode.
Also, a certain number of clock cycles, n_TRK, is required to ascertain
MC68HC908AB32 — Rev. 1.1
Freescale Semiconductor
Clock Generator Module (CGM)
Technical Data
155