MC908AB32CFUE Datasheet, PDF (325/392 Pages) Freescale Semiconductor, Inc – Microcontrollers

Input/Output (I/O) Ports
When DDRDx is a logic 1, reading address $0003 reads the PTDx data
latch. When DDRDx is a logic 0, reading address $0003 reads the
voltage level on the pin. The data latch can always be written, regardless
of the state of its data direction bit.
Table 17-5 summarizes the operation of the port D pins.
Table 17-5. Port D Pin Functions
DDRD
Bit
0
PTD Bit
X⁽¹⁾
I/O Pin
Mode
Input, Hi-Z⁽²⁾
Accesses
to DDRD
Read/Write
DDRD[7:0]
1
X
Output
DDRD[7:0]
Notes:
1. X = don’t care.
2. Hi-Z = high impedance.
3. Writing affects data register, but does not affect the input.
17.6.3 Port D Input Pullup Enable Register (PTDPUE)
Accesses to PTD
Read
Pin
PTD[7:0]
Write
PTD[7:0]⁽³⁾
PTD[7:0]
The port D input pullup enable register (PTDPUE) controls the input
pullup device for each of the eight port D pins. Each bit is individually
configurable and requires that the data direction register, DDRD, bit be
configured as an input. Each pullup is automatically and dynamically
disabled when a port bit’s DDRD is configured for output mode.
Address: $003D
Bit 7
6
5
4
3
2
1
Bit 0
Read:
PTDPUE7 PTDPUE6 PTDPUE5 PTDPUE4 PTDPUE3 PTDPUE2 PTDPUE1 PTDPUE0
Write:
Reset: 0
0
0
0
0
0
0
0
Figure 17-14. Port D Input Pullup Enable Register (PTDPUE)
PTDPUE[7:0] — Port D Input Pullup Enable Bits
These writable bits are software programmable to enable pullup
devices on an input port pin.
1 = Corresponding port D pin configured to have internal pullup
0 = Corresponding port D pin internal pullup disconnected
MC68HC908AB32 — Rev. 1.1
Freescale Semiconductor
Input/Output (I/O) Ports
Technical Data
325