W65C22S Datasheet, PDF (9/46 Pages) List of Unclassifed Manufacturers – Versatile Interface Adapter (VIA)

The Western Design Center, Inc.
W65C22S Data Sheet
When reading PA or PB, the contents of the corresponding Input Register (IRA or IRB) is transferred onto the Data Bus.
When the input latching feature is disabled, IRA will reflect the logic levels present on the PA bus lines. However, with
input latching enabled and the selected active transition on Peripheral A Control 1 (CA1) having occurred, IRA will
contain the data present on the PA bus lines at the time of the transition. In this case, once IRA has been read, it will
appear transparent, reflecting the current state of the PA bus lines until the next CA1 latching transition.
With respect to IRB, it operates similar to IRA except that for those PB bus lines that have been programmed as outputs,
there is a difference. When reading IRA, the logic level on the bus line determines whether a Logic 1 or 0 is sensed.
However, when reading IRB, the logic level stored in ORB is the logic level sensed. For this reason, those outputs which
have large loading effects may cause the reading of IRA to result in the reading of a Logic 0 when a 1 was actually
programmed, and reading Logic 1 when a 0 was programmed. However, when reading IRB, the logic level read will be
correct, regardless of loading on the particular bus line.
For information on formats and operation of the PA and PB registers, see Tables 1-2, 1-3 & 1-4. Note that the input
latching modes are controlled by the Auxiliary Control Register (See Table 1-8).
Table 1-2 ORB, IRB Operation for Register 0 ($00)
7
6
5
4
3
2
1
0
ORB,IRB
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
Pin Data Direction
Selection
DDRB="1" (Output)
WRITE
MPU writes Output Level (ORB)
DDRB="0" (Input)
(Input latching disabled)
DDRB="0" (Input)
(Input latching enabled)
MPU writes onto ORB, but no
effect on pin level, until DDRB
changed.
READ
MPU reads output register bit in ORB. Pin
level has no effect.
MPU reads input level
on PB pin.
MPU reads IRB bit, which is the level of the
PB pin at the time of the last CB1 active
transition.
The Western Design Center
W65C22S
9