W65C22S Datasheet, PDF (31/46 Pages) List of Unclassifed Manufacturers – Versatile Interface Adapter (VIA)

The Western Design Center, Inc.
Table 2-1 Pin Function Table
Pin
CA1, CA2
CB1, CB2
CS1, CS2B
D0-D7
IRQB
PA0-PA7
PB0-PB7
PHI2
RESB
RS0-RS3
R/WB
VDD
VSS
Description
Peripheral A Control Lines
Peripheral B Control Lines
Chip Select
Data Bus
Interrupt Request
Peripheral I/O Port A
Peripheral I/O Port B
Phase 2 Internal Clock
Reset
Register Select
Read/Write
Positive Power Supply (+5V)
Internal Logic Ground
W65C22S Data Sheet
2.1 Peripheral Data Port A Control Lines. (CA1, CA2)
CA1 and CA2 serve as interrupt inputs or handshake outputs for PA. Each line controls an internal Interrupt Flag
with a corresponding Interrupt Enable bit. CA1 also controls the latching of Input Data on PA. CA1 and CA2 are
high impedance CMOS inputs with a bus holding device. In the output mode, CA2 will drive one standard TTL
load.
2.2 Peripheral Data Port B Control Lines. (CB1, CB2)
CB1 and CB2 serve as interrupt inputs or handshake outputs for PB. Like PA, these two control lines control an
internal Interrupt Flag with a corresponding Interrupt Enable bit. These lines also serve as a serial data port under
control of the SR. Each control line represents a CMOS input with a bus holding device in the input mode and can
drive one TTL load in the output mode.
The Western Design Center
W65C22S
31