W65C22S Datasheet, PDF (25/46 Pages) List of Unclassifed Manufacturers – Versatile Interface Adapter (VIA)

The Western Design Center, Inc.
W65C22S Data Sheet
1.13.4
Shift Out - External CB1 Clock Control (111)
In the mode, shifting is controlled by external pulses applied to the CB1 line. The SR Counter sets IFR2 for
each eight-pulse count, but does not disable the shifting function. Each time the microprocessor reads or
writes the SR, IFR2 is reset and the counter is initialized to begin counting the next eight pulses on the CB1
line. After eight shift pulses, IFR2 is set. The microprocessor can then load the SR with the next eight bits
of data. See Figure 1-12.
PHI2
CLOCK
WRITE SR
OPERATION
CB1 OUTPUT
SHIFT CLOCK
CB2 OUTPUT
DATA
IRQB
1
1
2
2
8
8
Figure 1-12 Shift Out - External CB1 Clock Control Timing
1.14.
Interrupt Operation
There are three basic interrupt operations, including: setting the interrupt flag within IFR, enabling the interrupt by
way of a corresponding bit in the IER, and signaling the microprocessor using IRQB. An Interrupt Flag can be set
by conditions internal to the chip or by inputs to the chip from external sources. Normally, an Interrupt Flag will
remain set until the interrupt is serviced. To determine the source of an interrupt, the microprocessor must examine
each flag in order, from highest to lowest priority. This is accomplished by reading the contents of the IFR into the
microprocessor accumulator, shifting the contents either left or right and then using conditional branch instructions
to detect an active interrupt. Each Interrupt Flag has a corresponding Interrupt Enable bit in the IER. The enable
bits are controlled by the microprocessor (set or reset). If an Interrupt Flag is a Logic 1, and the corresponding
Interrupt Enable bit is a Logic 1, the IRQB will go to a Logic 0. IRQB is a full output driver that allows both Logic
1 and Logic 0 levels. The older NMOS and CMOS IRQB output was open drain pull down only. The IRQB output
cannot be wired-ORed with other devices.
All Interrupt Flags are contained within a single IFR. Bit 7 of this register will be Logic 1 whenever an Interrupt
Flag is set, thus allowing convenient polling of several devices within a system to determine the source of the
interrupt.
The Western Design Center
W65C22S
25