W65C22S Datasheet, PDF (21/46 Pages) List of Unclassifed Manufacturers – Versatile Interface Adapter (VIA)

The Western Design Center, Inc.
W65C22S Data Sheet
Table 1-10 Shift Register and Auxiliary Control Register Control ($0A)
7
6
5
4
3
2
1
0
SR
SR7
SR6
SR5
SR4
SR3
SR2
SR1
SR0
7 6 5 4 3 2 1 0 ACR
Shift Register
Mode Control
Shift Register Control
4 3 2 Operation
0 0 0 Disabled
0 0 1 Shift in under control of T2
0 1 0 Shift in under control of PHI2
0 1 1 Shift in under control of external clock (CB1)
1 0 0 Shift out free-running at T2 rate
1 0 1 Shift out under control of T2
1 1 0 Shift out under control of PHI2
1 1 1 Shift out under control of external clock (CB1)
Notes: 1. When shifting out, bit 7 is the first bit out and simultaneously is rotated back into bit 0.
2.
When shifting in, bits initially enter bit 0 and are shifted towards bit 7.
1.12. Shift Register Input Modes.
1.12.1
Shift Register Disabled (000)
In the 000 mode, the SR is disabled from all operation. The microprocessor can read or write the SR, but
shifting is disabled and both CB1 and CB2 are controlled by bits in the PCR. The Shift Register Interrupt
Flag (IFR2) is held low (disabled).
The Western Design Center
W65C22S
21