W65C22S Datasheet, PDF (15/46 Pages) List of Unclassifed Manufacturers – Versatile Interface Adapter (VIA)

The Western Design Center, Inc.
W65C22S Data Sheet
Table 1-6 T1 Counter Format and Operation1 ($04,$05)
7
6
5
4
3
2
1
0 T1L
128
64
32
16
8
4
2
1
WRITE -
READ -
8 bits loaded into T1 low-order latches. Latch contents are transferred into low-order counter at
the time the high-order counter is loaded.
8 bits from T1 low-order counter transferred to MPU. T1 interrupt flag IFR6 is reset.
7
6
5
4
3
2
1
0 T1H
32,768 16,384 8,192 4,096 2,048 1,024
512
256
WRITE -
READ -
8 bits loaded into T1 high-order latches. Also, both high and low-order latches are transferred
into T1 counter and this initiates countdown. T1 interrupt flag IFR6 is reset.
8 bits from T1 high-order counter transferred to MPU.
Table 1-7 T1 Latch Format and Operation1 ($06,$07)
7
6
5
4
3
2
1
0 T1L
128
WRITE -
READ -
64
32
16
8
4
2
1
8 bits loaded into T1 low-order latches. This operation is no different than a write into theT1
Low Order Register.
8 bits from T1 low-order latches transferred to MPU. Unlike reading the T1 Low Order
Register, this does not cause reset of T1 interrupt flag IFR6.
7
6
5
4
3
2
1
0 T1H
32,768 16,384 8,192 4,096 2,048 1,024 512
256
WRITE -
READ -
8 bits loaded into T1 high-order latches. Unlike writing to the T1 Low Order Register, no latch-
to-counter transfers take place. T1 interrupt flag IFR6 is reset.
8 bits from T1 high-order counter transferred to MPU.
The Western Design Center
W65C22S
15